MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

Browse source

Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

...

This commit is contained in:

Maciej W. Rozycki 2015-05-27 14:15:20 +01:00 • committed by Ralf Baechle

parent 3bcb03f3a7

commit 9a20b09285

1 changed files with 2 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

arch/mips/mm/tlb-r3k.c

View file