RISC-V: Avoid using per cpu array for ordered booting

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Currently both order booting and spinwait approach uses a per cpu
array to update stack & task pointer. This approach will not work for the
following cases.
1. If NR_CPUs are configured to be less than highest hart id.
2. A platform has sparse hartid.

This issue can be fixed for ordered booting as the booting cpu brings up
one cpu at a time using SBI HSM extension which has opaque parameter
that is unused until now.

Introduce a common secondary boot data structure that can store the stack
and task pointer. Secondary harts will use this data while booting up
to setup the sp & tp.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

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Atish Patra 2022-01-20 01:09:13 -08:00 • committed by Palmer Dabbelt

parent 3938d5a2f9

commit 9a2451f186

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4 changed files with 58 additions and 15 deletions

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25

arch/riscv/include/asm/cpu_ops_sbi.h

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3

arch/riscv/kernel/asm-offsets.c

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24

arch/riscv/kernel/cpu_ops_sbi.c

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19

arch/riscv/kernel/head.S

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