drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3

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So store into the scratch space of the HWS to make sure the invalidate
occurs.

v2: use GTT address space for store, clean up #defines (Chris)
v3: use correct #define in blt ring flush (Chris)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Jesse Barnes 2012-10-26 09:42:42 -07:00 • committed by Daniel Vetter

parent 12f3382bc0

commit 9a28977181

3 changed files with 26 additions and 6 deletions

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8

drivers/gpu/drm/i915/i915_reg.h

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22

drivers/gpu/drm/i915/intel_ringbuffer.c

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2

drivers/gpu/drm/i915/intel_ringbuffer.h

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