clk: sunxi: mod1 clock support

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The module 1 type of clocks consist of a gate and a mux and are used on
the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
SPDIF. This commit adds support for them on the sunxi clock driver.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>

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Emilio López 2014-07-18 15:28:02 -03:00 • committed by Maxime Ripard

parent e2771545f4

commit 9b038bc58a

2 changed files with 82 additions and 0 deletions

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1

drivers/clk/sunxi/Makefile

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81

drivers/clk/sunxi/clk-a10-mod1.c

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