arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core

Browse source

Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

...

This commit is contained in:

Fabrizio Castro 2018-12-14 09:10:13 +00:00 • committed by Simon Horman

parent 8d68821ced

commit 9b55a05ebf

1 changed files with 17 additions and 8 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

25

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

View file