drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS

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[Why]
If two monitors with TMDS signals were timing synced and one was
disconnected, the stream would go out of sync too early due to
the PLL turning off and the system could hang

[How]
On link disable output, change PHY FSM transition from TX_EN-to-PHY_OFF
to TX_EN-to-PLL_ON for TMDS

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Ryan Seto <ryanseto@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Ryan Seto 2024-09-13 16:01:47 -04:00 • committed by Alex Deucher

parent d1f8315fc8

commit 9b68445eb6

4 changed files with 57 additions and 82 deletions

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81

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

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52

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

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4

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

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2

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

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