cxgb4: Fix T5 adapter accessing T4 adapter registers

Browse source

Fixes few register access for both T4 and T5.
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS & PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS
is T4 only register don't let T5 access them. For T5 MA_PARITY_ERROR_STATUS2
is additionally read. MPS_TRC_RSS_CONTROL is T4 only register, for T5 use
MPS_T5_TRC_RSS_CONTROL.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

...

This commit is contained in:

Hariprasad Shenai 2014-09-01 19:54:57 +05:30 • committed by David S. Miller

parent 63a92fe6f7

commit 9bb59b96ae

3 changed files with 24 additions and 11 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

View file

29

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

View file

2

drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

View file