clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset

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[ Upstream commit e0f253a52c ]

To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.

Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.

Fixes: 35b97bb941 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Andre Przywara 2024-10-01 11:50:16 +01:00 • committed by Greg Kroah-Hartman

parent 4799f3f8fd

commit 9bc7ccfbd3

1 changed files with 1 additions and 1 deletions

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drivers/clk/sunxi-ng/ccu-sun20i-d1.c

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