pwm: meson: Fix the G12A AO clock parents order

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The Amlogic G12A and G12B Documentation is wrong, the AO xtal and clk81
clock source order is reversed, and validated when adding DVFS support
by using the PWM AO D output to control the CPU supply voltage.

The vendor tree also uses the reversed xtal and clk81 order at [1].

[1] https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/drivers/amlogic/pwm/pwm_meson.c#L462

Fixes: f41efceb46 ("pwm: meson: Add clock source configuration for Meson G12A")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

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Neil Armstrong 2019-06-20 16:46:55 +02:00 • committed by Thierry Reding

parent 1cdb44135d

commit 9bce02ef0d

1 changed files with 11 additions and 2 deletions

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drivers/pwm/pwm-meson.c

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