drm/amd/display: Fix TMDS 4K@60Hz YCbCr420 corruption issue

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[Why]
DIG_FIFO_OUTPUT_PIXEL_MODE not being set for dcn314
resulting in incorrect timing for YCbCr4:2:0

[How]
Copy the implementation of set_pixels_per_cycle from dcn32
over to dcn314

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Daniel Miess <Daniel.Miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Daniel Miess 2022-07-19 11:43:28 -04:00 • committed by Alex Deucher

parent 0cd34ce82b

commit 9bd110ab06

3 changed files with 34 additions and 0 deletions

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28

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

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4

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

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2

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c

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