drm/nouveau/fifo/nvc0-: use interrupt 31 as an event trigger

Browse source

Generated if you try and use fifo method 0x20 on any subchannel, appears
that it can be safely masked off without stalling the whole GPU.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

...

This commit is contained in:

Ben Skeggs 2013-01-31 13:51:20 +10:00

parent 1d7c71a3e2

commit 9bd2ddbaa2

4 changed files with 56 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

6

drivers/gpu/drm/nouveau/core/engine/fifo/base.c

View file

24

drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

View file

27

drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

View file

2

drivers/gpu/drm/nouveau/core/include/engine/fifo.h

View file