perf_counter: Fix up P6 PMU details

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The P6 doesn't seem to support cache ref/hit/miss counts, so
we extend the generic hardware event codes to have 0 and -1
mean the same thing as for the generic cache events.

Furthermore, it turns out the 0 event does not count
(that is, its reported that on PPro it actually does count
something), therefore use a event configuration that's
specified not to count to disable the counters.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

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Peter Zijlstra 2009-07-08 10:21:41 +02:00 • committed by Ingo Molnar

parent 11d1578f94

commit 9c74fb5086

1 changed files with 23 additions and 5 deletions

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arch/x86/kernel/cpu/perf_counter.c

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