media: platform: rzg2l-cru: rzg2l-ip: Add delay after D-PHY reset

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As per section 35.3.1 Starting Reception for the MIPI CSI-2 Input on the
latest hardware manual (R01UH0914EJ0140 Rev.1.40) it is mentioned that
after DPHY reset, we need to wait for 1 msec or more before start
receiving data from the sensor. So add a delay after pre_streamon().

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20240213181233.242316-3-biju.das.jz@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

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Biju Das 2024-02-13 18:12:30 +00:00 • committed by Hans Verkuil

parent f243df0a0b

commit 9c7fa014ca

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drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c

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