spi: spi-microchip-core: Add support for GPIO based CS

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The SPI "hard" controller within the PolarFire SoC is capable of
handling eight CS lines, but only one CS line is wired. Therefore, use
GPIO descriptors to configure additional CS lines.

Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Link: https://msgid.link/r/20240514104508.938448-4-prajna.rajendrakumar@microchip.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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Prajna Rajendra Kumar 2024-05-14 11:45:08 +01:00 • committed by Mark Brown

parent a7ed3a1120

commit 9c84429324

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drivers/spi/spi-microchip-core.c

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