drm/i915: Store the /5 target clock in struct dpll on vlv/chv

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Unify vlv/chv with earlier platforms so that the sturct dpll::dot
represents the /5 clock frequency (ie. DP symbol rate or HDMI
TMDS rate) rather than the *5 fast clock (/2 of the bitrate).
Makes life a little less confusing to get the same number back
in .dot which we fed into the DPLL algorithm.

v2: Actually just include the 5x in the final P divider
    Do the same change to the hand rolled gvt code
v3: Missed a few *5 in *_find_best_dpll()

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309214301.22899-1-ville.syrjala@linux.intel.com

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This commit is contained in:

Ville Syrjälä 2022-03-09 23:43:01 +02:00

parent 8d8b2dd399

commit 9ca48a806c

2 changed files with 12 additions and 15 deletions

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23

drivers/gpu/drm/i915/display/intel_dpll.c

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4

drivers/gpu/drm/i915/gvt/handlers.c

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