PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space

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Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>

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Bharat Kumar Gogada 2016-08-09 19:30:09 +05:30 • committed by Rob Herring

parent c4dcd205eb

commit 9cbbae2a62

1 changed files with 3 additions and 2 deletions

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Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt

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