drm/i915: fix for WaDisableDopClockGating:bdw

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This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.

v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170212133252.20990-1-robert@sixbynine.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

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Robert Bragg 2017-02-12 13:32:52 +00:00 • committed by Ville Syrjälä

parent a937eaf824

commit 9cc19733fd

2 changed files with 13 additions and 1 deletions

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8

drivers/gpu/drm/i915/intel_pm.c

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6

drivers/gpu/drm/i915/intel_ringbuffer.c

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