clk: samsung: exynos7: add gate clock for DMA block

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Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Padmavathi Venna 2015-01-13 16:57:40 +05:30 • committed by Sylwester Nawrocki

parent 83f191a7cd

commit 9cc2a0c95f

2 changed files with 7 additions and 1 deletions

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4

drivers/clk/samsung/clk-exynos7.c

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4

include/dt-bindings/clock/exynos7-clk.h

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