spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

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While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.

Fixes: 9ac8d17694 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Steve Wilkins <steve.wilkins@raymarine.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy
Signed-off-by: Mark Brown <broonie@kernel.org>

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Steve Wilkins 2024-07-15 12:13:56 +01:00 • committed by Mark Brown

parent 3a5e762836

commit 9cf71eb0fa

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drivers/spi/spi-microchip-core.c

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