clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

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The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Taniya Das 2019-02-11 13:09:28 +05:30 • committed by Stephen Boyd

parent 96dc791d0b

commit 9d575719ca

1 changed files with 1 additions and 0 deletions

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drivers/clk/qcom/gcc-qcs404.c

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