KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs

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Extend the existing FGT/FGU infrastructure to include the GICv5 trap
registers (ICH_HFGRTR_EL2, ICH_HFGWTR_EL2, ICH_HFGITR_EL2). This
involves mapping the trap registers and their bits to the
corresponding feature that introduces them (FEAT_GCIE for all, in this
case), and mapping each trap bit to the system register/instruction
controlled by it.

As of this change, none of the GICv5 instructions or register accesses
are being trapped.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-14-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

...

This commit is contained in:

Sascha Bischoff 2026-03-19 15:53:05 +00:00 • committed by Marc Zyngier

parent a258a383b9

commit 9d6d9514c0

8 changed files with 215 additions and 7 deletions

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19

arch/arm64/include/asm/kvm_host.h

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3

arch/arm64/include/asm/vncr_mapping.h

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3

arch/arm64/kvm/arm.c

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arch/arm64/kvm/config.c

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arch/arm64/kvm/emulate-nested.c

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arch/arm64/kvm/hyp/include/hyp/switch.h

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arch/arm64/kvm/hyp/nvhe/switch.c

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arch/arm64/kvm/sys_regs.c

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