clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

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1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
   add a variable to indicate this change and
   backward-compatible.

2. fmin: The PLL frequency lower-bound is vary from 1GHz to
   1.5GHz, add a variable to indicate platform-dependent.

Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

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Owen Chen 2019-03-05 13:05:40 +08:00 • committed by Stephen Boyd

parent a3ae549917

commit 9d7e1a82b7

2 changed files with 13 additions and 4 deletions

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2

drivers/clk/mediatek/clk-mtk.h

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15

drivers/clk/mediatek/clk-pll.c

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