[ARM] 4128/1: Architecture compliant TTBR changing sequence

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On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Catalin Marinas 2007-02-05 14:47:40 +01:00 • committed by Russell King

parent 620879c9e3

commit 9d99df4b10

1 changed files with 10 additions and 2 deletions

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arch/arm/mm/context.c

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