clk: Ingenic: Adjust cgu code to make it compatible with X1830.

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The PLL of X1830 Soc from Ingenic has been greatly changed,
the bypass control is placed in another register, so now two
registers may needed to control the PLL. To this end, a new
"bypass_reg" was introduced. In addition, when calculating
rate, the PLL of X1830 introduced an extra 2x multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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This commit is contained in:

周琰杰 (Zhou Yanjie) 2020-05-28 11:15:44 +08:00 • committed by Stephen Boyd

parent 15e3ae36f7

commit 9d9cc58aff

7 changed files with 41 additions and 4 deletions

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16

drivers/clk/ingenic/cgu.c

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4

drivers/clk/ingenic/cgu.h

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4

drivers/clk/ingenic/jz4725b-cgu.c

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4

drivers/clk/ingenic/jz4740-cgu.c

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8

drivers/clk/ingenic/jz4770-cgu.c

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3

drivers/clk/ingenic/jz4780-cgu.c

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6

drivers/clk/ingenic/x1000-cgu.c

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