drm/i915: Modify DP set clock to accomodate more eDP timings v2

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eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate.  Create a structure to store the DPLL divisor data to improve
readability.

v2: Fix the gen4_dpll/pch_dpll initialization to C99
designated initializers, and use a single loop for all platforms. (Jani and Daniel)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch warnings.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Chon Ming Lee 2013-09-04 01:30:37 +08:00 • committed by Daniel Vetter

parent 8807e55b3a

commit 9dd4ffdf39

1 changed files with 35 additions and 28 deletions

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drivers/gpu/drm/i915/intel_dp.c

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