drm/amd/display: Fix 3dlut size for Fastloading on DCN401

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[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.

[HOW]
Add register write to make valid.

Acked-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Adam Nelson <adnelson@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Adam Nelson 2024-04-09 17:38:44 -04:00 • committed by Alex Deucher

parent 3ecb039847

commit 9de99fa8c1

4 changed files with 17 additions and 0 deletions

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8

drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c

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5

drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h

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3

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

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1

drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h

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