ARM: dts: BCM63xx: fix L2 cache properties

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The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.

Fixes: 46d4bca044 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

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Florian Fainelli 2015-02-10 17:33:07 -08:00

parent 97bf6af1f9

commit 9df11828d9

1 changed files with 3 additions and 2 deletions

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arch/arm/boot/dts/bcm63138.dtsi

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