clk: bcm2835: Mark the CM SDRAM clock's parent as critical

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While the SDRAM is being driven by its dedicated PLL most of the time,
there is a little loop running in the firmware that periodically turns
on the CM SDRAM clock (using its pre-initialized parent) and switches
SDRAM to using the CM clock to do PVT recalibration.

This avoids system hangs if we choose SDRAM's parent for some other
clock, then disable that clock.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Eric Anholt 2016-06-01 12:05:35 -07:00 • committed by Stephen Boyd

parent eddcbe8398

commit 9e400c5cc5

1 changed files with 25 additions and 0 deletions

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drivers/clk/bcm/clk-bcm2835.c

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