clk: meson: meson8b: Add the vid_pll_lvds_en gate clock

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HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to
work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where
this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of
the HDMI PLL uses it's own set of registers it's more likely that this
"LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out"
clock to the "vid_pll_in_sel" tree.

Add a gate definition for this bit (which will not be exported) so that
the kernel can manage all required bits to enable and disable the video
clocks.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20210713232510.3057750-3-martin.blumenstingl@googlemail.com

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Martin Blumenstingl 2021-07-14 01:25:06 +02:00 • committed by Jerome Brunet

parent 1792bdac34

commit 9e544b75b2

2 changed files with 24 additions and 2 deletions

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23

drivers/clk/meson/meson8b.c

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3

drivers/clk/meson/meson8b.h

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