clk: renesas: rcar-gen4: Clarify custom PLL clock support

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The custom clock driver that models the PLL clocks on R-Car Gen4 assumes
the integer and fractional[*] multiplication field sizes as used on
R-Car V4H and V4M, representing a fractional 8.25 number.

Rename the related definitions, functions, and structures to clarify
this, and to prepare for the advent of support for the different field
sizes on R-Car S4-8.

[*] The fractional part is not yet supported.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/2ce9f9c75bfb6312129d416672f9691bbd11c0e7.1721648548.git.geert+renesas@glider.be

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Geert Uytterhoeven 2024-07-22 13:50:22 +02:00

parent 4897930deb

commit 9edc5c209d

1 changed files with 17 additions and 15 deletions

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drivers/clk/renesas/rcar-gen4-cpg.c

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