drm/i915: Use fixed offset for PTEs location

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We assumed that for all modern GENs the PTEs and register space are
split in the GTTMMADR BAR, but while it is true, we should rather use
fixed offset as it is defined in the specification.

Bspec: 4409, 4457, 4604, 11181, 9027, 13246, 13321, 44980

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210926201005.1450-1-michal.wajdeczko@intel.com

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Michal Wajdeczko 2021-09-26 22:10:05 +02:00 • committed by Matt Roper

parent 068396bb21

commit 9eddd5a9a2

1 changed files with 17 additions and 2 deletions

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19

drivers/gpu/drm/i915/gt/intel_ggtt.c

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