clk: renesas: div6: Restore clock state during resume

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On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
clock configuration.  Register an (optional) notifier to restore the
DIV6 clock state during system resume.

As DIV6 clocks can be picky w.r.t. modifying multiple register fields at
once, restore is not implemented by blindly restoring the register
value, but by using the existing cpg_div6_clock_{en,dis}able() helpers.

Note that this does not yet support DIV6 clocks with multiple parents,
which do not exist on R-Car Gen3 SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

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Geert Uytterhoeven 2017-06-21 22:34:33 +02:00

parent 1f4023cdd1

commit 9f8c71e513

3 changed files with 40 additions and 4 deletions

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38

drivers/clk/renesas/clk-div6.c

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3

drivers/clk/renesas/clk-div6.h

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3

drivers/clk/renesas/renesas-cpg-mssr.c

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