drm/msm/a6xx: Send the right perf index value to GMU

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The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

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Sharat Masetty 2018-09-27 22:16:22 +05:30 • committed by Rob Clark

parent b689a830f5

commit 9fb4bfd0be

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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