clk: imx: add pfdv2 support

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The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.

NOTE pfdv2 can only be operated when clk is gated.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[sboyd@kernel.org: Include clk.h for sparse warnings]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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A.s. Dong 2018-11-14 13:01:47 +00:00 • committed by Stephen Boyd

parent d9a8f950b2

commit 9fcb6be3b6

3 changed files with 208 additions and 1 deletions

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3

drivers/clk/imx/Makefile

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203

drivers/clk/imx/clk-pfdv2.c

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3

drivers/clk/imx/clk.h

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