net: dsa: sja1105: Take PTP egress timestamp by port, not mgmt slot

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The PTP egress timestamp N must be captured from register PTPEGR_TS[n],
where n = 2 * PORT + TSREG. There are 10 PTPEGR_TS registers, 2 per
port. We are only using TSREG=0.

As opposed to the management slots, which are 4 in number
(SJA1105_NUM_PORTS, minus the CPU port). Any management frame (which
includes PTP frames) can be sent to any non-CPU port through any
management slot. When the CPU port is not the last port (#4), there will
be a mismatch between the slot and the port number.

Luckily, the only mainline occurrence with this switch
(arch/arm/boot/dts/ls1021a-tsn.dts) does have the CPU port as #4, so the
issue did not manifest itself thus far.

Fixes: 47ed985e97 ("net: dsa: sja1105: Add logic for TX timestamping")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Vladimir Oltean 2019-12-27 02:59:54 +02:00 • committed by David S. Miller

parent 0caeaf6ad5

commit 9fcf024dd6

2 changed files with 3 additions and 3 deletions

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2

drivers/net/dsa/sja1105/sja1105_main.c

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4

drivers/net/dsa/sja1105/sja1105_ptp.c

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