drm/i915/chv: Add DPIO offset for Cherryview. v3

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CHV has 2 display phys.  First phy (IOSF offset 0x1A) has two channels,
and second phy (IOSF offset 0x12) has single channel.  The first phy is
used for port B and port C, while second phy is only for port D.

v2: Move the pipe to determine which phy to select for
vlv_dpio_read/vlv_dpio_write to another patch. (Daniel)
v3: Rebase the code based on rework on how to calculate DPIO offset.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Chon Ming Lee 2014-04-09 13:28:14 +03:00 • committed by Daniel Vetter

parent c294c545f7

commit a09cadddde

3 changed files with 13 additions and 2 deletions

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2

drivers/gpu/drm/i915/i915_drv.h

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1

drivers/gpu/drm/i915/i915_reg.h

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12

drivers/gpu/drm/i915/intel_display.c

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