drm/i915: ValleyView mode setting limits and PLL functions

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Add some VLV limit structures and update the PLL code.

v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits
v3: re-add dpio write function
v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Jesse Barnes 2012-06-15 11:55:13 -07:00 • committed by Daniel Vetter

parent cc889e0f6c

commit a0c4da24ea

2 changed files with 239 additions and 2 deletions

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1

drivers/gpu/drm/i915/i915_reg.h

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240

drivers/gpu/drm/i915/intel_display.c

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