clk: renesas: r9a07g044: Add clock and reset entry for SCI1

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Add clock and reset entry for SCI1 interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2021-11-03 16:05:37 +00:00 • committed by Geert Uytterhoeven

parent 099ee03271

commit a0d2a2c673

1 changed files with 3 additions and 0 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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