cxl/pci: Prepare for mapping RAS Capability Structure

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The RAS Capabilitiy Structure is a CXL Component register capability
block. Unlike the HDM Decoder Capability, it will be referenced by the
cxl_pci driver in response to PCIe AER events. Due to this it is no
longer the case that cxl_map_component_regs() can assume that it should
map all component registers. Plumb a bitmask of capability ids to map
through cxl_map_component_regs().

For symmetry cxl_probe_device_regs() is updated to populate @id in
'struct cxl_reg_map' even though cxl_map_device_regs() does not have a
need to map a subset of the device registers per caller.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974412214.1608150.11487843455070795378.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

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This commit is contained in:

Dan Williams 2022-11-29 10:48:42 -07:00

parent 920d8d2c60

commit a1554e9cac

3 changed files with 31 additions and 12 deletions

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3

drivers/cxl/core/hdm.c

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34

drivers/cxl/core/regs.c

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4

drivers/cxl/cxl.h

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