dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms

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The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

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Daniel Lezcano 2025-12-08 03:08:18 +01:00 • committed by Jonathan Cameron

parent 048a15b721

commit a19489ca82

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Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml

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