drm/amd/display: Program self refresh control register on boot

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[WHY]
In headless boot cases, self refresh control registers are not
programmed on boot. In certain hybrid graphics cases this may cause
cstate entering to get blocked causing a hang.

[HOW]
Program self refresh control register on boot.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Sung Lee 2020-01-30 11:54:52 -05:00 • committed by Alex Deucher

parent 201a94469f

commit a19620ea91

1 changed files with 3 additions and 0 deletions

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drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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