coresight-etm4x: Conditionally access register TRCEXTINSELR

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[ Upstream commit dcdc42f5dc ]

The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0.
To avoid invalid accesses, introduce a check on numextinsel
(derived from TRCIDR5[11:9]) before reading or writing to this register.

Fixes: f5bd523690 ("coresight: etm4x: Convert all register accesses")
Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250812-trcextinselr_issue-v2-1-e6eb121dfcf4@oss.qualcomm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Yuanfang Zhang 2025-08-12 01:24:45 -07:00 • committed by Greg Kroah-Hartman

parent ad58a89bb5

commit a1b2c8b7af

2 changed files with 10 additions and 3 deletions

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11

drivers/hwtracing/coresight/coresight-etm4x-core.c

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2

drivers/hwtracing/coresight/coresight-etm4x.h

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