clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

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The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC.
The only difference being that RZ/V2L has additional registers to
control clocks and resets for the DRP-AI block.

Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same
between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take
care of the DRP-AI clocks/resets.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Biju Das 2022-02-05 08:40:06 +00:00 • committed by Geert Uytterhoeven

parent fbf4ae93c2

commit a1bcf50a99

5 changed files with 250 additions and 191 deletions

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7

drivers/clk/renesas/Kconfig

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1

drivers/clk/renesas/Makefile

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426

drivers/clk/renesas/r9a07g044-cpg.c

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6

drivers/clk/renesas/rzg2l-cpg.c

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1

drivers/clk/renesas/rzg2l-cpg.h

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