diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 54f5311ed016..f2c4bc900e5f 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -43,6 +43,7 @@ properties: - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 + - qcom,apss-wdt-x1e80100 - const: qcom,kpss-wdt - const: qcom,kpss-wdt deprecated: true diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 7815ece261ea..76b93b7bd50f 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -1643,8 +1643,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-07000200", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; interrupts = ; @@ -2287,6 +2291,47 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1c3 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1c4 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1c5 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1c6 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1c7 0x0>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 01434f8a5300..db65c392e618 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -8360,6 +8360,14 @@ }; }; + apss_watchdog: watchdog@17410000 { + compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; + reg = <0x0 0x17410000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + status = "reserved"; /* Reserved by Gunyah */ + }; + cpucp_mbox: mailbox@17430000 { compatible = "qcom,x1e80100-cpucp-mbox"; reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d3a25a837488..e39743e22043 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1945,8 +1945,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, @@ -2449,8 +2449,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 6251189b8e6d..a2907f8a6376 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -1070,7 +1070,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1288,7 +1288,7 @@ pinctrl-0 = <&sdc1_default>; pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1313,7 +1313,7 @@ pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1517,8 +1517,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8917_VDDCX>, - <&rpmpd MSM8917_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi index c94eb14e31bd..7de6447de48f 100644 --- a/arch/arm64/boot/dts/qcom/msm8937.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -1122,7 +1122,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1210,7 +1210,7 @@ phys = <&mdss_dsi1_phy>; operating-points-v2 = <&mdss_dsi1_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1457,7 +1457,7 @@ pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1487,7 +1487,7 @@ pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1710,8 +1710,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8937_VDDCX>, - <&rpmpd MSM8937_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 76317c578349..753167c3f861 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -545,6 +545,20 @@ interrupt-controller; #interrupt-cells = <2>; + i2c_1_default: i2c-1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + i2c_1_sleep: i2c-1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + uart_console_active: uart-console-active-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -559,6 +573,311 @@ bias-pull-down; }; + i2c_2_default: i2c-2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_sleep: i2c-2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_3_default: spi-3-default-state { + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_3_sleep: spi-3-sleep-state { + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c_3_default: i2c-3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_sleep: i2c-3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_default: i2c-4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_sleep: i2c-4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_5_default: spi-5-default-state { + cs-pins { + pins = "gpio18"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_5_sleep: spi-5-sleep-state { + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + uart_5_default: uart-5-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + drive-strength = <16>; + bias-disable; + }; + + uart_5_sleep: uart-5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_default: i2c-5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_sleep: i2c-5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_6_default: spi-6-default-state { + cs-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_6_sleep: spi-6-sleep-state { + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c_6_default: i2c-6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_sleep: i2c-6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gpio_key_default: gpio-key-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c_8_default: i2c-8-default-state { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_sleep: i2c-8-sleep-state { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_on: cd-on-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_default: i2c-7-default-state { + pins = "gpio135", "gpio136"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_sleep: i2c-7-sleep-state { + pins = "gpio135", "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_7_default: spi-7-default-state { + cs-pins { + pins = "gpio136"; + function = "blsp_spi7"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "blsp_spi7"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_7_sleep: spi-7-sleep-state { + cs-pins { + pins = "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + sdc1_clk_on: sdc1-clk-on-state { pins = "sdc1_clk"; bias-disable; @@ -640,312 +959,6 @@ bias-pull-up; drive-strength = <2>; }; - - sdc2_cd_on: cd-on-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - sdc2_cd_off: cd-off-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - gpio_key_default: gpio-key-default-state { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c_1_default: i2c-1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - i2c_1_sleep: i2c-1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_2_default: i2c-2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - i2c_2_sleep: i2c-2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_default: i2c-3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_sleep: i2c-3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_default: i2c-4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_sleep: i2c-4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_default: i2c-5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_sleep: i2c-5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_default: i2c-6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_sleep: i2c-6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_7_default: i2c-7-default-state { - pins = "gpio135", "gpio136"; - function = "blsp_i2c7"; - drive-strength = <2>; - bias-disable; - }; - - i2c_7_sleep: i2c-7-sleep-state { - pins = "gpio135", "gpio136"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_8_default: i2c-8-default-state { - pins = "gpio98", "gpio99"; - function = "blsp_i2c8"; - drive-strength = <2>; - bias-disable; - }; - - i2c_8_sleep: i2c-8-sleep-state { - pins = "gpio98", "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi_3_default: spi-3-default-state { - cs-pins { - pins = "gpio10"; - function = "blsp_spi3"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_3_sleep: spi-3-sleep-state { - cs-pins { - pins = "gpio10"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_5_default: spi-5-default-state { - cs-pins { - pins = "gpio18"; - function = "blsp_spi5"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_5_sleep: spi-5-sleep-state { - cs-pins { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_6_default: spi-6-default-state { - cs-pins { - pins = "gpio22"; - function = "blsp_spi6"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_6_sleep: spi-6-sleep-state { - cs-pins { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_7_default: spi-7-default-state { - cs-pins { - pins = "gpio136"; - function = "blsp_spi7"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio135", "gpio137", "gpio138"; - function = "blsp_spi7"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_7_sleep: spi-7-sleep-state { - cs-pins { - pins = "gpio136"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio135", "gpio137", "gpio138"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - uart_5_default: uart-5-default-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "blsp_uart5"; - drive-strength = <16>; - bias-disable; - }; - - uart_5_sleep: uart-5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcnss_pin_a: wcnss-active-state { - - wcss-wlan2-pins { - pins = "gpio76"; - function = "wcss_wlan2"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan1-pins { - pins = "gpio77"; - function = "wcss_wlan1"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan0-pins { - pins = "gpio78"; - function = "wcss_wlan0"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan-pins { - pins = "gpio79", "gpio80"; - function = "wcss_wlan"; - drive-strength = <6>; - bias-pull-up; - }; - }; }; gcc: clock-controller@1800000 { @@ -1201,6 +1214,49 @@ }; }; + cci: cci@1b0c000 { + compatible = "qcom,msm8953-cci"; + reg = <0x1b0c000 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-506.0", "qcom,adreno"; reg = <0x01c00000 0x40000>; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index f9962512f243..80a0a09e055d 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1558,8 +1558,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8976_VDDCX>, - <&rpmpd MSM8976_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5c75fba16ce2..d41b5c470c48 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1497,8 +1497,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd MSM8998_VDDCX>, - <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; status = "disabled"; @@ -1544,7 +1544,7 @@ interrupts = ; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { @@ -1680,7 +1680,7 @@ qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_SSCCX>; + power-domains = <&rpmpd RPMPD_SSCCX>; power-domain-names = "ssc_cx"; status = "disabled"; @@ -2871,7 +2871,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2953,7 +2953,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -3029,7 +3029,7 @@ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; @@ -3277,7 +3277,7 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 4a72e0718fe4..f4b8e8f468f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1058,8 +1058,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd SDM660_VDDCX>, - <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; @@ -1096,7 +1096,7 @@ "rbcpr", "core"; - power-domains = <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; iommus = <&kgsl_smmu 0>; nvmem-cells = <&gpu_speed_bin>; @@ -1401,7 +1401,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; pinctrl-1 = <&sdc2_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; status = "disabled"; @@ -1455,7 +1455,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <8>; non-removable; @@ -1618,7 +1618,7 @@ "rotator-mem"; iommus = <&mmss_smmu 0>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1670,7 +1670,7 @@ reg-names = "dsi_ctrl"; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <4>; @@ -2359,7 +2359,7 @@ clock-names = "xo"; memory-region = <&adsp_region>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; qcom,smem-states = <&adsp_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 55a45b528bd3..0edb2992b902 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -36,6 +36,42 @@ }; }; + vreg_cam_af_2p85: regulator-cam-af-2p85 { + compatible = "regulator-fixed"; + regulator-name = "cam_af_2p85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam_io_1p8: regulator-cam-io-1p8 { + compatible = "regulator-fixed"; + regulator-name = "cam_io_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam2_dig_1p2: regulator-cam2-dig-1p2 { + compatible = "regulator-fixed"; + regulator-name = "cam2_dig_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ lcdb_dummy: regulator-lcdb-dummy { compatible = "regulator-fixed"; @@ -52,6 +88,27 @@ }; }; +&cci { + status = "okay"; +}; + +&cci_i2c0 { + /* Sony IMX363 (rear) @ 0x10 */ + + eeprom@50 { + compatible = "belling,bl24s64", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_cam_io_1p8>; + read-only; + }; + + /* ON Semi LC898217 VCM @ 0x72 */ +}; + +&cci_i2c1 { + /* Samsung S5K4H7YX (front) @ 0x10 */ +}; + &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index c252f248ef15..3fd6dd82a992 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -194,7 +194,7 @@ /* DSI1 shares the OPP table with DSI0 */ operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <5>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index dcaea15c6d43..c7e5268cc3fa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -45,6 +45,8 @@ }; &i2c4 { + clock-frequency = <100000>; + status = "okay"; max98927_codec: max98927@3a { diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 88513b513871..e9336adbc391 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1715,8 +1715,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-610.0", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 8f2d65543373..80c42dff5399 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -724,7 +724,7 @@ clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x160 0x0>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040873>; @@ -755,7 +755,7 @@ pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040873>; @@ -1275,7 +1275,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1345,7 +1345,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -1406,7 +1406,7 @@ "ref"; required-opps = <&rpmpd_opp_nom>; - power-domains = <&rpmpd SM6125_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; }; @@ -1434,7 +1434,7 @@ "gcc_disp_gpll0_div_clk_src"; required-opps = <&rpmpd_opp_ret>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f34dc6e278b8..9f9b9f9af0da 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1117,6 +1117,7 @@ reg = <0x0 0x016e0000 0x0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -1124,6 +1125,8 @@ reg = <0x0 0x01700000 0x0 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; compute_noc: interconnect-compute-noc { compatible = "qcom,sm6350-compute-noc"; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a76bf5193a70..f56b1f889b85 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -540,6 +541,14 @@ reg = <0x0 0xff800000 0x0 0x800000>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + reusable; + }; }; smp2p-adsp { @@ -2214,6 +2223,66 @@ qcom,remote-pid = <2>; label = "lpass"; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1048 0x20>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; @@ -3505,6 +3574,947 @@ #reset-cells = <1>; }; + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x37280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_in0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_aoss_in7>; + }; + }; + }; + }; + + tpdm@10800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint = <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@10803000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10803000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_modem_in0: endpoint { + remote-endpoint = <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_modem_in1: endpoint { + remote-endpoint = <&tpdm_modem1_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint = <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@10804000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10804000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint = <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint = <&tn_ag_in13>; + }; + }; + }; + }; + + cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1080b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@1082c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1082c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint = <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@10841000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10841000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint = <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@1084e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_bcv_out: endpoint { + remote-endpoint = <&tpda_mm_in0>; + }; + }; + }; + }; + + tpdm@1084f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_lmh_out: endpoint { + remote-endpoint = <&tpda_mm_in1>; + }; + }; + }; + }; + + tpdm@10850000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10850000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_dpm_out: endpoint { + remote-endpoint = <&tpda_mm_in2>; + }; + }; + }; + }; + + tpda@10851000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10851000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_mm_in0: endpoint { + remote-endpoint = <&tpdm_mm_bcv_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_mm_in1: endpoint { + remote-endpoint = <&tpdm_mm_lmh_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_mm_in2: endpoint { + remote-endpoint = <&tpdm_mm_dpm_out>; + }; + }; + }; + + out-ports { + port { + tpda_mm_out: endpoint { + remote-endpoint = <&tn_ag_in4>; + }; + }; + }; + }; + + tpdm@10980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10980000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpda@10986000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10986000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint = <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint = <&tpdm_cdsp_llm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@10987000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10987000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1098b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@109a3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint = <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@109a4000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_ipcc_cmb_out: endpoint { + remote-endpoint = <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@109a5000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dl_mm_out: endpoint { + remote-endpoint = <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@109a6000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a6000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@109a7000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a7000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@109a8000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a8000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@109a9000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a9000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@109aa000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109aa000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in32>; + }; + }; + }; + }; + + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x109ab000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + tn_ag_in4: endpoint { + remote-endpoint = <&tpda_mm_out>; + }; + }; + + port@d { + reg = <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint = <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg = <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint = <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg = <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint = <&tpdm_prng_out>; + }; + }; + + port@13 { + reg = <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@19 { + reg = <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint = <&tpdm_dl_mm_out>; + }; + }; + + port@1a { + reg = <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint = <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg = <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint = <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg = <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb_out>; + }; + }; + + port@1d { + reg = <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint = <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg = <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg = <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg = <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb2_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@109d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tn_ag_in19>; + }; + }; + }; + }; + + funnel@10b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint = <&tpda_aoss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_aoss_in7: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@10b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@10b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint = <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint = <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint = <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint = <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint =<&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint = <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@10b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint = <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@10b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint = <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@10b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint = <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@10b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint = <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@10b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint = <&tpda_aoss_in4>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; @@ -4457,4 +5467,43 @@ , ; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint = <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible = "qcom,coresight-static-tpdm"; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint = <&tpda_modem_in1>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index d956c91c7cc8..88980d8c3ee3 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -532,7 +532,6 @@ qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; - opp-shared; opp-75000000 { opp-hz = /bits/ 64 <75000000>; diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 2d1c9151cf1b..175679be01eb 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -7,6 +7,10 @@ /dts-v1/; /plugin/; +&apss_watchdog { + status = "okay"; +}; + /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ &gpu_zap_shader { status = "disabled";