staging: dwc2: properly mask the GRXFSIZ register

Bits 16-31 are reserved, so the old code just reads the whole register to
get bits 0-15, assuming the reserved bits would be 0 (which seems true
on current hardware, but who knows...).

This commit properly masks out the reserved bits when reading and
doesn't touch the reserved bits while writing.

Signed-off-by: Matthijs Kooijman <matthijs@stdin.nl>
Acked-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matthijs Kooijman 2013-08-30 18:45:20 +02:00 • committed by Greg Kroah-Hartman
commit a1fc524393
2 changed files with 18 additions and 7 deletions