clk: renesas: r9a07g044: Add clock and reset entries for CRU

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Add CRU clock and reset entries to CPG driver.

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g044_no_pm_mod_clks[] array and pass it as part of CPG data for
both RZ/G2L and RZ/V2L SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221221212703.348278-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2022-12-21 21:27:03 +00:00 • committed by Geert Uytterhoeven

parent d969103ac8

commit a278d0c92b

1 changed files with 25 additions and 1 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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