drm/amd/display: fix pixel rate update sequence

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The k1/k2 pixel rate dividers in dccg should only be updated on stream enable
and do not actually depend on whether odm combine is active.

This removes an on flip update of these and fixes the calculate function
to ignore odm status for dp steams.

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Dmytro Laktyushkin 2023-06-01 16:09:32 -04:00 • committed by Alex Deucher

parent f4bc8a4306

commit a2c7356f52

6 changed files with 7 additions and 27 deletions

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11

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

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9

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c

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2

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h

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8

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

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2

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h

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2

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h

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