riscv: dts: renesas: r9a07g043f: Add L2 cache node

Browse source

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

...

This commit is contained in:

Lad Prabhakar 2023-09-29 01:07:00 +01:00 • committed by Geert Uytterhoeven

parent 587c848ac3

commit a38b1061d3

1 changed files with 12 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

12

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

View file