drm/amd/display: fix inputting clk lvl into dml for RN

Browse source

[Why]
Previous logic is only good for 15W parts. Other configuration
need a smarter logic to match clk levels with pp table in the fuse.

[How]
Cache all 8 DPM level's clock data, find lvl that match each pstate
in the pp table and build input into DML base on that

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Eric Yang 2020-01-20 12:56:43 -05:00 • committed by Alex Deucher

parent 71b81f1275

commit a39a581669

2 changed files with 127 additions and 41 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

165

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

View file

3

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

View file