[MIPS] SB1: Fix interrupt disable hazard.

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The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Ralf Baechle 2006-03-13 16:16:29 +00:00

parent 3a2f735700

commit a3c4946db4

1 changed files with 103 additions and 77 deletions

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186

include/asm-mips/hazards.h

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